unix - rules for makefile -

let's assume have makefile unix

prog:a.o b.o c.o     gcc a.o b.o c.o -o prog a.o:a.c a.h b.h     gcc -c a.c b.o:b.c b.h     gcc -c b.c c.o:c.c c.h b.h     gcc -c c.c 

i read if change *.c file must recompile file, if change *.h file must recompile files depending on *.h file, after both cases anyway i must link files beginning

1)let's assume change b.h, need do? variant make a.o b.o c.o right?

2)let's assume change c.c, need do? variant make c.o right?

and if write make c.o example makefile only recompile c.o what linker? have gcc -c c.c , not -o

thanks in advance help

what mean 'what need do?'. in every case, run make prog, , let make figure out, that's whole point.

edit: if you're curious make in each case, assuming you're running make prog every time, read on:

in case 1) b.h has changed, depending on (a.o, b.o , c.o) rebuilt, , prog relinked.

in case 2) c.o direct dependency of c.c, c.o built , prog relinked.

btw, gcc can give it's take on dependencies running gcc -mm *.c in project directory.