xilinx - Why IEEE vhdl standard library is not STL? -

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ieee vhdl language reference manual defined limited set of standard packages.and not defined functionalities on standard types,such std_logic.so there no standard and2, inv components/operator.

it seems altera's max+plus ii not support and2, inv component(if there are,please feel free correct me),but xilinx foundation does.

why ieee vhdl standard library not become stl in c++ world?

thanks.

invert, and, or,... std_logic types are supported ieee libraries:

a <= b , c d <= not e f <= g or h

your synthesis tool automatically translate these expressions best implementation target technology (xilinx fpga, altera fpga, asic, ...). there no need explicitly instantiate technology specific components. instantiating technology specific components might obstruct optimizations.

you should try write vhdl code technology independent. allows reuse code.


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